The present invention relates to a Phase Locked Loop (PLL) circuit and, more particularly, to a PLL circuit employed in a frequency synthesizer tuning system.
For a purpose of the realization of the multichannel or the digital communication such as a cordless telephone and a portable communication equipment, a frequency synthesizer tuning system employing a PLL circuit is widely used. The PLL circuit operates to tune a system to a desired channel and hence is required to have a high response speed. The time needed to switch the current channel over to a new channel, i.e. frequency-locking time, is thereby shortened.
The PLL circuit includes a phase comparator and a loop filter to control the oscillation frequency of a voltage controlled oscillator (VCO) by comparing in phase a reference signal with a signal from a counter for dividing the oscillation signal of the VCO. The frequency-locking time thereby depends on the response speed of the PLL circuit. The transient response speed is determined by a loop gain, a natural angular frequency and a damping factor of the PLL circuit. Among these factors, the loop gain has the dominant input/output characteristic of the VCO and the phase comparator, and the damping factor mainly depends on a time constant of the loop filter.
When the loop filter comprises an active type filter having an operational amplifier, an input resistor and a feedback circuit, the natural angular frequency .omega.n and the damping factor .zeta. are represented as follows: ##EQU1##
where Ko and Kv denote the phase comparator gain and the VCO conversion gain, respectively, and R1, C1 and R2 represent an input impedance, a feedback capacity and a resistance of the active filter. The damping factor depends on two time constants C1-R1 and C1.R2. In general, to make the frequency-locking time small, the damping factor .zeta. is set to approximately 0.7.
Referring to FIG. 7 showing an example of the transient response speed of a PLL circuit, when the damping factor .zeta. is set to be large, for example, 2.0, since the natural angular frequency .omega.n is also large, the first transition rapidly occurs. Although the time to shift from the initial frequency fo1 to the set frequency fo2 is short, the compensation sensitivity with respect to a minute frequency deviation is low and hence the convergence time to obtain the final stable state is long, thereby taking a long locking time TL. Further, since the equivalent noise band width of the loop is large, the noise component in the high frequency of the VCO can not be sufficiently eliminated, the carrier/noise ratio (C/N ratio) is thus deteriorated.
When the damping factor .zeta. is small, for example, 0.3, the natural angular frequency .omega.n is also small, the first transition delays and hence the time to shift from the initial frequency fo1 to the set frequency fo2 is long, thereby resulting in the long locking time TL. When the damping factor .zeta. is in the vicinity of 0.7, the time to shift from the initial frequency fo1 to the set frequency fo2 is moderate. However, the compensation sensitivity with respect to the frequency deviation is high, the convergence time to obtain the final stable state is hence short, realizing the minimum locking time TL.
Referring to FIG. 6, a conventional PLL circuit includes a synthesizer unit 1, an active type filter 2 as a loop filter which generates a voltage control signal VC in response to a control signal CP from the unit 1, and a VCO 3 for outputting an oscillation signal 0 in response to the voltage control signal VC. This signal 0 is used for tuning. The unit 1 has a phase comparator 11 for carrying out the phase comparison between a reference signal R and a frequency division signal F to output a phase error signal D, a charge pump circuit 12 for converting the phase error signal D into the control signal CP, and a frequency-divider 13 which receives the oscillation signal 0 and divides it by a frequency division ratio set therein to produce the frequency division signal F. The filter 2 includes an inverting operational amplifier A1, an input resistor R1, and a feedback circuit composed of a resistor R2 and a capacitor C1 which are connected in series between the input and output of the inverting amplifier A1.
The PLL circuit as shown in FIG. 6 operates to lock the frequency division signal F in phase with the reference signal R. Accordingly, the VCO 3 produces a signal 0 having a frequency fo which is equal to the frequency fr of the reference signal R multiplied by N, i.e., fo=N.times.fr, wherein N indicates the frequency-division ratio set into the divider 13. When the frequency division ratio N of the divider 13 is changed from the first frequency division ratio N1 to N2 in order to tune to another channel, the frequency of the frequency division signal F is varied accordingly. The phase comparator 11 thereby detects a difference in phase between the reference signal R and the varied frequency division signal F and produces the signal D indicative of that difference. This signal D causes the VCO to change the frequency of the oscillation signal 0 through the charge pump circuit 12 and the filter 2. As a result, the VCO 3 oscillates and produces the signal 0 having a oscillation frequency fo2 that is equal to N2 .times.fr.
The respective values of the capacitor C1 and resistors R1 and R2 correspond to C1, R1 and R2 of the equation (2), respectively, and thus selected such that the damping factor .zeta. is in the vicinity of 0.7, as described above.
The frequency-locking time of the PLL circuit is, however, constant. The frequency-locking time is required to be further shortened for the multichannelization of a tuner.
To this end, a PLL circuit is disclosed in Japanese Patent Laid-open Publication No. Hei 2-94710 in which the reference signal frequency is raised only when the transient state (unlocked state) at the time of frequency switching and again lowered to the original frequency after the locking. Another PLL circuit is shown in Japanese Patent Laid-open Publication No. Sho 60-16731, Japanese Patent Laid-open Publication No. Sho 62-92521 and Japanese Patent Laid-open Publication No. Hei 3-191642, for the purpose of adopting the two-mode damping factor switching system in which the damping factor is switched by means of the charge pump circuit, the switches and others in accordance with the locked or unlocked state before and after the locking of the PLL in order to achieve both the optimization of the locking time.
Thus, although various types of PLL circuits are proposed, there are many performance degradation factors such as the unstable locking when the frequency switching or the malfunction due to the jittering and the adjustment is difficult. Moreover, it is impossible to reduce the locking time determined by an optimum value of the loop constant more than ever.